Note: The job is a remote job and is open to candidates in USA. Paradigm Works, Inc. delivers world-class chip development services and software for digital integrated circuits. They are seeking a UVM Verification Engineer to develop and maintain testbenches, create test plans, and collaborate with various teams to ensure the correctness of RTL designs.
Responsibilities
- Develop and maintain SystemVerilog/UVM testbenches, including stimulus generation, checkers, monitors, and scoreboards to verify complex RTL designs
- Creating test plans
- Writing and executing tests
- Debugging simulation failures
- Collaborating closely with design, validation, and architecture teams to ensure functional correctness and coverage goals
- Analyzing verification results
- Tracking defects
- Refining test environments
- Contributing to continuous improvement of verification methodologies and automation
- Mentoring other team members
- Reviewing verification collateral
- Supporting client-facing technical discussions when needed
Skills
- AI experience or interest in learning AI for verification
- Strong RTL Design and Functional Verification skills, including experience with SystemVerilog and UVM
- Proficiency in Debugging and Validation of complex digital designs using simulation and related tools
- Understanding of Good Manufacturing Practice (GMP) or similar quality and process compliance frameworks, where applicable
- Experience with EDA tools (simulators, waveform viewers, coverage tools) and version control systems
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Ability to work effectively in a remote, distributed team, with clear written and verbal communication skills
- Familiarity with scripting languages (e.g., Python, Perl, or shell) to automate verification workflows is beneficial
- Background in ASIC/SoC design flows and knowledge of standard bus protocols (e.g., AXI, PCIe) is a plus
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